The present invention relates in general to computing systems and more particularly to systems and methods for providing security for computing systems having a processing unit, such as a microprocessor, with one or more processor components such as cache units, instruction cache units, branch prediction units, branch target buffers, and other components.
Over the years, various techniques have been developed for protecting computing systems from unauthorized access. For example, techniques for protecting computing systems can be software and/or hardware based. Many of today's techniques are software based and target network intruders. Unfortunately, many conventional techniques today do not effectively protect computing systems from various types of security breaches. For example, the central processing units (CPUs) have recently been shown to cause unforeseen security vulnerabilities that threaten the entire computing system.
More recently, there have been increased research efforts concentrating on the security analysis of computing systems by analyzing the vulnerabilities due to the functional behavior of microprocessor components such as branch prediction units. As described above, computing systems are often vulnerable to security breaches at the processor level. More specifically, it is well-known that microprocessor components such as instruction cache and branch prediction units create significant security weaknesses.
Branch prediction is an important aspect of modern computing and is used in virtually all computing systems. Typically, a branch prediction unit (BPU) is an integral part of the central processing unit (CPU) and its functions include determining whether a conditional branch in the instruction flow of a program or process is likely to be taken or not. As shown in FIG. 1, a conventional BPU 10 typically includes a branch predictor 20 and a branch target buffer (BTB) 50. The BPU 10 uses both the BTB 50 and branch predictor 20 to assist the CPU in performing speculative execution, e.g., by deciding the most likely execution path after a conditional branch.
In conventional computer architectures, the predictor 20 is a part of the BPU that makes the prediction on the outcome of the branch. The predictor usually is a unit that predicts the most likely execution path after a conditional branch by trying to find repetitive patterns in the history of the conditional branch. For example, there are different parts of a predictor 20, including, but not limited to, branch history registers (BHR) 30 such as global history registers and local history registers, and branch prediction tables 40.
In various computer architectures, the BTB 50 is the buffer where the CPU stores the target addresses of the previously executed branches. Because this buffer is limited in size, the CPU can only store a limited number of such target addresses. For example, a previously stored address may be replaced by a new address if the new address needs to be stored. Typically, a buffer is implemented by an array of registers, each register location holding the logical value of 1 or 0. If the CPU cannot find the target address of a branch in the BTB, it has to compute the address. Typically, the computation process imposes a performance cost, as the CPU cannot immediately feed the pipeline with instructions from the correct path.
As an important component of the CPU, the state of the BPU affects the execution of a process in a CPU. Often, an attacker is able to predict the state transitions during the execution of a process, as these transitions cause observable effects. For example, typically the execution time of a process, the power consumption of the processor (thus the power consumption of the entire system), the electromagnetic dissipation of the processor (thus the entire system), etc. depend on the state of microprocessor components such as the BPU, data cache, instruction cache and the like. The execution time also depends on the transitions of these states. Furthermore, typical microprocessors use special registers that keep track of these changes and store statistics related to these states transitions. Such registers can also be used to observe these states and state transitions. The ways to observe such information are not limited to these specific examples, and additional ways are known to those skilled in the art. The knowledge of these states and state transition gives an attacker the ability to predict the secret and/or hidden values used in a security mechanism or process. For example, it is possible to determine a secret value by checking whether a Montgomery multiplication executes the extra reduction during an RSA exponentiation.
As another example, an attacker may alter the state of the BPU, instruction cache and/or other components of a processor to cause measurable effects on the execution of a cipher process, which is, generally, an algorithm for performing encryption and decryption. These effects, especially those on the encryption time, can be directly or indirectly observed by an attacker and can be used to compromise the computer system and/or its security functions. In addition, the execution of the cipher process also affects the state transitions. For example, the cipher leaves its footprints when the instruction cache and BPU state changes depending on the execution. An attacker may examine these states to capture these footprints and obtain the secret values if the execution flow is key-dependent. In other words, an adversary can learn the execution flow of a cipher using BPU and/or instruction cache based attacks. If this execution flow depends on a key, for example, the attacker may be able to obtain the key and break into the computer system. The security vulnerabilities caused by the observable state and state transitions due to the functionalities of the processor components are not limited to the examples given herein.
Accordingly, it is desirable to provide improved security solutions for computing systems. In particular, it is desirable to provide better security solutions for protecting computing systems from attacks that exploit the state of the processor and system components and to protect against the security vulnerabilities due to the BPU operations.